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a quad +15v 256-position digital potentiometer with pin selectable spi/i 2 c digital interface preliminary technical data AD5263 rev. p r e 1/23 /03 i n f o rmat ion f u rnished by analog devices is beli e ved t o be accurat e and reliable. however, n o responsibil it y is assumed by analog devices f o r it s use; nor f o r any i n f r ingement s of pat ent s o n e t echn o l o g y w ay, p.o . b o x 9106, nor w ood, ma 02062-910 6 u . s . a . t e l : 781/ 329-4700 w o rld wi d e w e b si te: h t tp:/ /w ww . a n a lo g . c o m fe a t ures 4-ch ann el 25 6-positi on end-to-en d re sistance 2 0 k, 5 0 k, 200k ? pin selectable spi or i 2 c compatib le interfac e t w o p a ckag e address d e co de pins ad 0 a nd ad1 lo w t e mperat ure co efficient 30p pm/ o c w i de operati n g t e mperat ure rang e -40 to 125oc + 5 to + 15v single-s upp l y ; 7 .5v dua l -sup pl y oper ation a p plic a t ions mecha n ica l po tentiometer r e plac ement optical net w or k adjustment instrumentation: gain , offset adjustment stereo ch an ne l audi o lev el c ontrol automotive electronics adjustment programm abl e voltage to c u r r ent conv ersio n programm abl e f ilters, dela ys , t i me constan t s lin e imped anc e matchin g lo w r e sol u tio n dac re plac ement motor control gener a l de scription t he AD5263 is the industri e s first quad ch an nel, 25 6 positi on, di gital potentiom e ter 1 w i th a selecta b le d i gita l interface. t hese devic es perfo rm the same el ectronic adj ustment fun c tion as mech a n ical pote n tiom eters or va ri ab l e re si stors w i th en h anc ed reso lutio n , solid-st a te relia bi lit y , a nd super ior lo w te mperatur e coef ficient performa nce. each cha n n e l of the ad52 63 contai ns a fixe d resistor w i th a w i p e r cont act that taps the fixed resistor val ue a t a point deter mine d b y a di gi tal code loa ded i n to the 3- w i re spi or 2- w i re i 2 c com patib le seri al- inp u t register. t he resistance bet w e e n the w i per a nd either e nd p o in t of the fixed re sistor varies li n earl y w i t h respect to the digit a l cod e tra n sferred i n to th e rdac latch. t he variabl e resistor of fers a complet e l y progr ammab l e valu e of resista n ce, bet w e en t he a terminal and th e w i p e r or the b terminal a nd the w i p e r. t he fixed a to b terminal res i stance of 20k, 50k or 20 0k ? has a nom in al temper ature co efficient of 30 p p m/c. unlik e the maj o rit y of the d i git a l pote n tiom eters in the market, these devic es can o p e rate up to + 1 5 v or 7.5v . t he AD5263 is avail abl e in n a rro w bo d y t ssop-24. all parts are gu ara n teed to o perat e over the a u to motive temperatur e ra nge of -40 c to + 125c. not e 1. t he t e rms digit a l pot ent iomet e r, vr , and r d ac are used int e rchangeably. func ti on al b l ock di agr am a1 w 1 b 1 a2 w 2 b 2 a3 w 3 b 3 a4 w 4 b 4 rda c 1 regi st er rdac 2 reg i s t er rd a c 3 regi st er rdac 4 reg i s t er seri a l i n put reg i st er 8 clk / s cl sdi / sda cs /a d 0 v l gn d di s s do / o1 nc / o2 v dd sh dn rs /a d 1 v ss s p i / i 2 c selec t lo g i c ad dr ess de code r a d 52 63 0% 25% 50% 75% 100% 0 6 4 128 19 2 2 56 c o de - de c i m a l r wa (d ) , r wb ( d ) -% o f n o m i n a l r ab 255 r wa r wb r wa a nd r wb vs. co d e or ot her right s of t h ird part i es which may re sult f r om it s use. no license is grant ed by implicat ion or ot herwise under any pat ent or patent right s of analog devices. f ax: 781/ 326-8703 ? an a l og devi ces, i n c . , 2003
preliminary technical data AD5263 rev. pre 1/23/03 2 electrical characteris tics 20k, 50k, 200k : version (v dd = + 5v , v ss = -5v, v l = +5v , v a = +v dd , v b = 0v, -40c < t a < +125c unless otherwise noted.) parameter symbol conditions min typ 1 max units dc characteristics rheostat mode specifications apply to all vrs resistor differential nl 2 r-dnl r wb , v a =nc -1 1/4 +1 lsb resistor nonlinearity 2 r-inl r wb , v a =nc -2 1/2 +2 lsb nominal resistor tolerance 3 ' r ab t a = 25c -30 30 % resistance temperature coefficient ' r ab / ' t wiper = no connect 30 ppm/c wiper resistance r w i w = 1 v/r ab , v dd = +5v 50 100 : dc characteristics potentiometer divider mode specifications apply to all vrs resolution n 8 bits differential nonlinearity 4 dnl ?1 1/4 +1 lsb integral nonlinearity 4 inl ?2 1/2 +2 lsb voltage divider temper ature coefficient ' v w / ' t code = 80 h 5 ppm/c full-scale error v wfse code = ff h ?2 -1 +0 lsb zero-scale error v wzse code = 00 h 0 +1 +2 lsb resistor terminals voltage range 5 v a,b,w v ss v dd v capacitance 6 ax, bx c a,b f = 1 mhz, measured to gnd, code = 80 h tbd pf capacitance 6 wx c w f = 1 mhz, measured to gnd, code = 80 h tbd pf common-mode leakage i cm v a =v b = v dd / 2 1 na digital inputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v l = +3v, v ss = 0v 2.1 v input logic low v il v l = +3v, v ss = 0v 0.6 v input current i il v in = 0v or +5v 1 a input capacitance 6 c il 5 pf digital output o1, o2 v oh i oh =0.4ma, i 2 c mode 2.4 5.5 v o1, o2 v ol i ol =-1.6ma, i 2 c mode 0 0.4 v sdo v ol i ol = -6ma 0.6 v sdo v ol i ol = -3ma 0.4 v three-state leakage current i oz v in = 0v or +5v 1 a output capacitance 6 c oz 3 8 pf power supplies logic supply v l 2.7 5.5 v power single-supply range v dd range v ss = 0v 4.5 16.5 v power dual-supply range v dd/ss range 4.5 7.5 v logic supply current i l v l = +5v 60 a positive supply current i dd v ih = +5v or v il = 0v 1 a negative supply current i ss v ss = -5v 1 a power dissipation 9 p diss v ih = +5v or v il = 0v, v dd = +5v, v ss = -5v 0.6 mw power supply sensitivity pss ' v dd = +5v 10% 0.002 0.01 %/% dynamic characteristics 6, 10 bandwidth ?3db bw r ab = 20k/50k/200k : 400/tbd/tbd khz total harmonic distortion thd w v a =1vrms, v b = 0v, f=1khz, r ab = 20k : 0.05 % v w settling time t s v a = 10v, v b =0v, 1 lsb error band 2 s resistor noise voltage e n_wb r wb = 10k: , f = 1khz, rs = 0 9 nv ? hz
preliminary technical data AD5263 rev. pre 1/23/03 3 electrical characteristics 20k, 50k, 200k : version (v dd = + 5v , v ss = -5v, v l = +5v, v a = +v dd , v b = 0v, -40c < t a < +125c unless otherwise noted.) parameter symbol conditions min typ 1 max units spi interface timing characteristics applies to all parts (notes 6,10) clcok frequency f clk 25 mhz input clock pulse width t ch ,t cl clock level high or low 20 ns data setup time t ds 10 ns data hold time t dh 10 ns cs setup time t css 15 ns cs high pulse width t csw 20 ns clk fall to cs fall hold time t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock rise setup t cs1 10 ns reset pulsewidth t rs 5 ns i 2 c interface timing characteristics applies to all parts(notes 6,12) scl clock frequency f scl 400 khz t buf bus free time between stop & start t1 1.3 s t hd;sta hold time (repeated start) t2 after this period the first clock pulse is generated 0.6 s t low low period of scl clock t3 1.3 s t high high period of scl clock t4 0.6 50 s t su;sta setup time for start co ndition t5 0.6 s t hd;dat data hold time t6 0.9 s t su;dat data setup time t7 100 ns t f fall time of both sda & scl signals t8 300 ns t r rise time of both sda & scl signals t9 300 ns t su;sto setup time for stop condition t10 0.6 s notes: 1. typicals represent av erage readings at +25c and v dd = +5v, v ss = -5v. 2. resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd =+5v, v ss =-5v. 3. v ab = v dd , wiper (v w ) = no connect 4. inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. va = v dd and v b = 0v. dnl specification limits of 1lsb maximu m are guaranteed monotonic operating conditions. 5. resistor terminals a, b, w have no limitations on polarity with respect to each other. 6. guaranteed by design and not subject to production test. 7. measured at the ax terminals. all ax te rminals are open circuited in shutdown mode. 8. worst case supply current consumed when input all logic-input levels set at 2.4v, standard characteristic of cmos logic. 9. p diss is calculated from (i dd x v dd ). cmos logic level inputs result in minimum power dissipation. 10. all dynamic characteristics use v dd = +5v, v ss = -5v, v l = +5v . 11. measured at a v w pin where an adjacent v w pin is making a full-scale voltage change. 12. see timing diagram for location of measured values. all input control voltages are specified with t r =t f =2ns(10% to 90% of +3v) and timed from a voltage level of 1.5v. switching characteristics are measured using v l = +5v. 13. propagation delay depends on value of v dd , r l , and c l . 14. the AD5263 contains 5,184 transistors. die size: 108mil x 198mil, 21,384sq. mil.
preliminary technical data AD5263 rev. p r e 1/23 /03 4 a b solute ma ximum r a ti ngs 1 (t a = + 25c, unl ess other w i se not e d ) v dd to gnd .................................................. -0 .3, +16.5v v ss to gnd ....................................................... 0v, -7.5v v dd to v ss ............................................................. +16.5v v l to gnd ...................................................... -0.3, +6.5v v a , v b , v w to gnd ............................................ v ss , v dd a x ? b x , a x ? w x , b x ? w x intermittent 2 ............................................ 20ma continuous ............................................... 5ma digital inputs & output vo ltage to gnd ............. 0v, +7v operating t e m per ature range ............... - 40c to +85c maximum ju nc tion t e mperatu r e (t j max ) ........... +150c storage t e mperature ............................ -65c to +150 c lead t e mperatur e (soldering, 10 sec) ................ +300c vapor phase ( 60 sec) .............................. +215 c infrared (15 sec) ...................................... + 220 c t hermal resist ance 3 ja, t s s o p-24 ................................................ 143 c/w notes 1. st resses above t hos e list ed under absolut e maximum rat i ngs may cause permanent damage t o t he device. t h is is a s t ress rat i ng; funct i onal operat ion of t he device at t hese or any ot her condit i ons above t hose list ed in t he o per at ional sect ions of t h is specif icat ion is not implied. exposure to absolut e maximum rating condit i ons f o r ext ended periods may af f e ct device reliabilit y. 2. maximum t e rminal cu rrent is bounded by t he maximum current handling of t he swit ches , maximum power dissipat ion of t he package, an d maximum applied volt age across any t w o of t he a , b , and w t e rminals at a given resist ance 3. package power diss ipat ion (t jm ax -t a )/ t ja c a ution esd (electrost atic disch arge) sensitiv e devic e. el ectrostatic charges as h i g h as 400 0 v re adil y accumu late o n the huma n bo d y a nd test equ i p ment an d can dischar ge w i th out detecti on. althou gh the a d 52 63 featur e s propri e tar y e s d protectio n circuitr y , p e rm ane nt dama ge ma y occur on d e vic e s subj ected to high- ener g y el ectr ostatic disc harg e s. t herefore, prop er esd preca u tions are recomme nde d to avoid perf o rm anc e de gra datio n or loss o f functional it y .
preliminary technical data AD5263 ad 526 3 pin co nfig ur a t ion a d5 2 6 3 a 2 w1 b3 b4 b1 w2 b2 a 1 t s so p- 24 1 2 3 4 24 23 22 21 a 3 a 4 5 20 v ss gnd dis sdo/ o 1 w3 nc/o2 w4 v dd 6 7 8 9 19 18 17 16 v logic s hd n 10 15 sd i / sd a r s /a d 1 11 14 clk/ scl c s /a d 0 12 13 table vii: ad52 63 pin descriptio ns pin name des c ription 1 b1 resistor terminal b1 2 a1 resistor termi n a l a1 (add r=00) 3 w1 wip e r te rmina l w1 4 b3 resistor terminal b3 5 a3 resistor terminal a3 6 w3 wiper termin a l w3 (addr=10 ) 7 v dd positive p o w e r supp l y , sp ecifi ed for + 5 v to + 15v operati on 8 gnd ground 9 dis digita l interfac e select (spi/i 2 c select); spi w hen dis= ?0 ?, i 2 c w h e n dis=?1? 10 v logic log ic sup p l y v o ltag e, nee ds to be same volta ge a s the digita l lo g i c control lin g the ad52 63. 11 sdi/sda sdi = 3-w i re serial data input/ sda = 2-w i re serial data input/out put 12 clk/scl serial c l ock in put 13 cs /ad0 chip s e lect / i 2 c comp atabi le device a ddres s bit 0 14 rs /ad1 reset b/i 2 c c o mpata b il e de vice address bit 1 15 shdn shutdo w n -- t i es w i p e r to terminal a, opens termi nal b 16 sdo/o1 serial data output, open drain transistor req u i r es pul l-up resistor/dig ital output o1, can be used to driv e e x tern al l ogic 17 nc/o2 no co nnecti on /digital outp ut o2, can be us ed to drive e x tern al l ogic 18 v ss neg a tive p o w e r suppl y, spec ified for operati on from 0 to -5v. 19 w4 wiper termin a l w4 (addr=11 ) 20 a4 resistor terminal a4 21 b4 resistor terminal b4 22 w2 wiper termin a l w2 (addr=01 ) 23 a2 resistor terminal a2 24 b2 resistor terminal b2 mode l r ab (k : ) t e m p p a c k a g e descripti on package option # parts per conta i ner t op mark* ad52 63br u 2 0 2 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 6 2 ad52 63b 2 0 ad52 63br u 2 0 -reel 7 2 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 ad52 63b 2 0 ad52 63br u 5 0 5 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 6 2 ad52 63b 5 0 ad52 63br u 5 0 -reel 7 5 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 ad52 63b 5 0 ad52 63br u 2 0 0 2 0 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 6 2 ad52 63b 2 0 0 ad52 63br u 2 00-ree l 7 2 0 0 -40/+ 125 c t s s o p - 2 4 r u - 2 4 1 , 0 0 0 ad52 63b 2 0 0 *line 1 con t ain s pa rt n u mber, line 2 co ntain s ad i l ogo foll ow ed b y the end- to -end re si sta n ce , lin e 3 con t ain s date code y w w . rev. p r e 1/23 /03 5
preliminary technical data AD5263 rev. p r e 1/23 /03 6 spi compatible digital interface (dis=?0?) table i. AD5263 seri al-da t a word form at a ddr d a t a b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 m s b l s b 2 9 2 7 2 0 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 1 d 0 s d i c l k c s v o u t 0 1 0 1 0 1 0 1 d 2 r d a c r e g i s t e r l o ad figure 1a. a d 52 63 tim i ng diagra m (v a = 5v, v b = 0v, v w = v out ) t c s h 0 t c s s t c h t c l t d s t d h t c s h 1 t c s w t s 1 l s b s d i ( d a t a i n ) 0 1 0 1 0 1 0 v d d c l k c s v o u t d x d x t c s 1 f i gure 1b. detail ed t i mi n g dia gra m ( v a = 5v, v b = 0v, v w = v out )
preliminary technical data AD5263 rev. p r e 1/23 /03 7 i 2 c compatible digital interface (dis=?1?) table iia. write mode s 0 1 0 1 1 a d 1 a d 0 w a x a 1 a 0 r s s d o 1 o 2 x a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p slave ad dress b y te instruction b y t e data b y t e table iib. i 2 c read mo de data word f o rmat s 0 1 0 1 1 0 a d 0 r a d 7 d 8 d 5 d 4 d 3 d 2 d 1 d 0 a p slave ad dress b y te data b y t e s = start condi tion p = stop condi tion a = ackno w ledge ad 1 , a d 0 = packag e pi n pro g ramma ble a d d ress bits, mus t match w i t h the logic states at pins ad 1, ad0 a1 , a0 = rdac sub ad dress select rs = soft w a re reset w i per (a1, a0) to mid scale position sd = shutdo w n active hi gh, ti es w i p e r (a1, a0) to terminal a , ope ns termina l b, rdac regis t er contents ar e not disturb e d . t o exit shutdo w n a comma nd sd = ?0? must be e x ec uted fo r each r d ac (a 1, a0). w = write = ?0 ? r = read = ?1? d7,d6,d5,d4, d3,d2,d1,d0 = data bits x = don?t care t 4 sda scl s p t 1 t 2 t 3 t 7 t 6 t 5 t 8 t 8 t 9 t 10 t 9 p s f i gure 2. deta il ed t i min g dia g r am sc l sd a 1 9 1 0 1 1 0 ad0 ad 1 r / w ack. b y a d 526 3 d7 d6 d5 d3 d4 d0 d1 d2 1 9 ack. by ad 5 2 6 3 x a1 a0 s d rs x o2 o1 1 9 ac k. by a d 5 263 fr a m e 1 s l av e a dd r e s s b y t e st a r t b y m ast er fr a m e 2 i n st r u c t i o n b yt e fr a m e 3 d a ta by te st o p by ma s t e r f i gure 3 a . w r iting to the rda c regist er sc l sd a 1 9 1 0 1 1 0 ad 0 ad 1 r / w a c k. by a d 5 263 1 9 d7 d6 d5 d3 d4 d0 d1 d2 no ack . by m a s t e r fr am e 1 s l av e a ddr es s b y t e st ar t b y m aste r fr am e 2 d a t a b y t e fr om s e l e c t ed rd a cr e g is t er st o p by ma s t e r a f i gure 3 b . rea d in g data fro m a previous ly selecte d rdac regist er in w r ite mode
preliminary technical data AD5263 oper a t ion t he AD5263 is a quad c han n e l, 256- positi o n digita ll y- control l ed var i a b le res i stor (vr) devic e. t o program the vr settings, refer to the dig ital interface section. both p a rts have an i n te rnal p o w e r o n preset that plac es the w i p e r at mid-scal e durin g po w e r on, w h ic h simplifi e s the fault con d iti on r e cover y at po wer up. in add ition, the sh utdo w n shdn p i n of ad52 63 p l aces the rdac in an al most zero po w e r consum ptio n state w h ere terminal a is o pen circ uited a nd the w i per w is connecte d to terminal b, resulti ng in onl y leaka ge curre nt consum ption i n the vr structur e. durin g shut do w n , the vr latch settings a r e mainta ine d or ne w settin g s can be progr ammed. w hen the p a rt is returned from shutdo w n , the corresp on d i ng vr settin g w i ll b e ap pli ed to the rdac. r s d 5 d 4 d 3 d 2 d 1 d 0 r d a c l a t c h & d e c o d e r s h d n a x b x w x r s r s r s d 6 d 7 f i gure 4. ad52 63 eq uiva l ent rdac c i rcuit progr a mmi ng the v a ri a b le resist or rh eo stat op eratio n t he nominal re sistance of the rdac b e t w ee n termina ls a and b is ava i l a ble i n 20k, 50k, and 20 0k : . t he fina l t w o or three di gits of the part num ber determ i ne t he nom ina l resistanc e valu e, e.g. 20k : = 20; 50k : = 50; 200k : = 200. t he nomi nal res i stance ( r ab ) of the vr has 25 6 contact poi nts accesse d b y t h e w i p e r termin a l, plus the b terminal c ontac t. t he 8-bit data in the rda c latch is deco d e d to sel e ct one of the 256 p o ssi ble s e ttings. assume a 20k : part is used, the w i p e r' s first connecti on starts at the b termina l for dat a 00 h . sinc e there is a 60 : w i per cont act resistance, such con necti o n y i el ds a minimum of 60 : resistance b e t w e e n termin a ls w and b. t he second co nnecti on ? w ab wb r r d d r ? w h er e: d is the decimal e quiv a le nt of the binar y c ode l o a ded i n the 8-bit rdac register r ab is the end -to-end res i sta n ce r w is the w i p e r resistanc e contrib u ted b y t he on- resistance of the interna l s w itc h in summary , if r ab = 20k : a nd the a?termin a l is ope n circuite d, the follo w i n g outp u t resistanc e r wb w i ll be set for the follo w i ng rdac latch codes. table iii. codes a nd corresp ondi ng resi stan ce s d r wb output state (dec) ( : ) 255 199 82 f u ll-scal e (r ab - 1lsb + r w ) 128 100 60 mid-scal e 1 138 1 lsb 0 60 z e ro-scal e (w iper contact res i stance) note that in the zero-scal e con d itio n a finite w i per resistanc e of 60 : is prese n t. care sh oul d be taken to limit the current flo w b e t w e en w and b in this st ate to a maximum p u ls e current of no more than 2 0 m a . other w i s e , degr adati on or possi ble d e stru cti on of the inte rnal s w itc h contact can oc cur. similar to the mecha n ica l pot entiom e ter, the resistance of the rdac b e tw e e n the w i per w and termina l a also prod uces a d i gi tall y c ontro lle d compl e mentar y resista n ce r wa . w hen these termin a ls a r e used, the b? terminal c an be op en ed. set t ing the resista n ce val ue for r wa starts at a maximum va l ue of resistanc e and d e cre a s e s as the data loa ded i n the la tch increas es i n valu e. t he gener al equ atio n for this operati on is: (2) 256 256 ) ( w ab wa r r d d r ? fo r r ab = 20k : and b?term in al open circ uite d, the follo w i n g output resista n c e r wa w ill b e set for the follo w i ng rd ac latch cod e s (se e t able iv). rev. p r e 1/23 /03 8
preliminary technical data AD5263 table iv. codes a nd corresp ondi ng resi stan ce s d r wa output state (dec) ( : ) 255 138 f u ll-scal e 128 100 60 mid-scal e 1 199 82 1 lsb 0 200 60 z e ro-scal e t he ty p i cal d i stributi on of the end-to- e n d resi stance r ab from chann el-t o-cha nne l matches w i th in 1 %. device to devic e matchin g is process l o t depe nd ent an d is possi ble to have 3 0% variati on. sinc e the resistanc e elem ent is process ed in th in film techn o lo g y , the ch an ge in r ab wi t h temperatur e ha s a ver y l o w 30 ppm/c tempe r ature coefficient. progr a mmi ng the pote ntiometer divider vo ltag e ou tpu t op eratio n t he digital p o tentiom e ter eas il y ge nerates a voltag e divid e r at w i p e r - to-b and w i per -to-a to be pro portio nal to the inp u t voltag e at a-to-b. unlike the p o l a rit y of v dd -v ss , w h ich m u st be positiv e, volt ag e across a-b, w - a, and w - b can be at eith er pol arit y prov ide d that v ss is po w e r ed b y a neg ative su ppl y. if ignoring th e effect of the w i per resista n ce for appr o x imati on, connecti ng a? terminal to 5v and b? terminal to gr o und pr od uces an outp u t volta ge at the w i per-to-b start i ng at zero vo lts up to 1 lsb l e ss than 5v. each lsb of voltag e is eq ual to the voltag e app lie d across terminal ab d i v i de d b y th e 25 6 positi ons of the potenti o meter divid e r. since t he ad5 2 6 3 ca n be sup p l i ed b y dua l sup p li e s , the gener al equ atio n defin i ng the o u tput voltag e at v w w i th respect to groun d for any valid input voltag e ap pli e d to terminals a and b is: (3) 256 256 256 ) ( b a w v d v d d v f o r a more acc u rate calc ulati o n, w h ich i n clu d e s the effect of w i per res i sta n ce, v w can be found as: (4) 256 ) ( 256 ) ( ) ( b wa a wb w v d r v d r d v operatio n of the dig i tal p o t enti o meter in the d i vider mo de results in a more accurate o p e ratio n over te mperatur e. unlik e the rhe o s tat mode, t he output volt age i s depe nd ent mainl y on the r a tio of the inter nal res i stors r wa and r wb and n o t the ab solute va lu es, therefor e, t he temperatur e drift reduces to 5 ppm/c. pin sele c table di gital inter f ace t he AD5263 pr ovid es the fle x i b ilit y of a sel e c t able interface. whe n the dis(dig it al interface se l e ct) pin is tied lo w , the s p i mode is en g age d. w hen the dis pin is tied hi gh, the i 2 c mode is e n g age d. spi comp a t i b le 3-wire s e ri a l bus(dis = ?0?): t he AD5263 c ontai ns a three - w i re spi comp atibl e dig i tal interface (sdi, cs , and clk). t he 10-bit seri al w o r d must be lo ad ed w i th addr ess bits a1 and a0 fo llo w e d b y the data b y te msb first. t he format of the w o r d i s sho w n i n t able i. table v. AD5263 add r e s s de co de ta ble a1 a0 latch lo ad ed 0 0 rdac # 1 0 1 rdac # 2 1 0 rdac # 3 1 1 rdac # 4 t he positive-e dge se nsitiv e clk in put req u ires cle an transitio ns to avoid cl ockin g in correct data int o the seria l inp u t register. standar d lo gic families w o rk w e ll. if mecha n ica l s w i t ches are use d for product ev alu a tion th e y shou ld b e deb ounc ed b y a fli p -flop or oth e r suitab le means. w hen cs is lo w , the clock loads data into the serial register o n eac h positiv e clock edge (se e f i g u re 1a). table vi: input logic cont rol trut h tabl e clk cs rs shdn regist er activity l l h h no sr effect, enab les sdo pi n p l h h shift one bit in from the sdi pin. previo us ten bi ts are shifted o u t of the sdo pin. x p h h loa d sr data i n to rdac l a tch base d on a ddr ess deco der (t abl e v). x h h h no operati on x x l h sets all rda c latches to mids cale clears sdo lat c h. x h h l open circu i ts all resistor a? terminals, connects w to b , tu rns off sdo output transistor. note: p = p o sitive edge, x = don 't care, sr = shift register t he data setup and dat a hol d times in the sp ecificati on table d e termin e the vali d timi ng req u irem ent s. t he ad52 63 us es a 10-b i t serial i nput dat a regis t er w o r d that is transferred to the inter nal r d a c register w h en the cs lin e returns to log i c high. an y e x tra bits are ig nor ed. also, as cs goes hi gh, it activates the a ddress d e co de r and upd ates the co rrespo ndi ng ch ann el d u ri ng sh u t dow n( shdn ), the sdo output pi n is forced to logic hig h in or der to avoi d po w e r dissi pati o n in the ext e rna l pul l up resistor. f o r equiv a le nt sdo output circu i t schematic (se e f i gure 5). rev. p r e 1/23 /03 9
preliminary technical data AD5263 s e r i a l r e g i s t e r d q c k r s s d o s h d n c s s d i c l k r e s f i gure 5. deta iled s d o outpu t schematic of the ad5 2 6 3 dais y - ch ain op eratio n t he serial data output (sdo) pin co ntai ns an open dr ai n n- chan nel f e t . t h is output req u ires a p u ll- up resistor in order to transfe r data to the ne xt pack age' s s d i pin. t h is allo w s f o r dais y ch ain i ng s e veral rda cs fro m a singl e process o r seri al data l i n e . t he pul l-up res i stor terminati on voltag e can b e larg er than the v dd sup p l y vo ltage. it is recomme nde d to increas e the clock peri od w hen us in g a pull- up res i stor to the sdi pin of the follo w i n g device beca u se ca pac itive lo adi ng at the dais y -c hai n node sdo- sdi bet w e en devices may induce time delay to subse q u ent de vices. users sh oul d be a w a r e of this potenti a l pr obl em to achiev e data transfer s u ccessful l y (see f i gur e 6). if t w o ad 526 3 s are dais y -c ha ine d , a total of 20 bits of da ta is requir ed. t he first 10 bits, compl y in g w i t h the format sho w n i n t able i, go to u2 and the sec ond 10 bits w i th the same format go to u1. cs shoul d be ke pt lo w u n til al l 20 bits are clock e d into their res pective ser i al registers. after this, the cs is pulled high to complete the oper ation and l oad the r d ac latch. a d 5 2 6 3 s d i s d o c s c l k a d 5 2 6 3 s d i s d o c s c l k 2 . 2 k : r p v d d u 1 u 2 s c l m o s i s d p c a f i gure 6. da is y-chai n co nfig u r ation i 2 c comp a t i b le 2-wire seri a l bus( d is = ?1?): t he AD5263 is controll ed via an i 2 c compatible ser i al bus. t he rdacs are conn ected to this bus as sla v e devic es. referrin g to f i gures 2 a nd 3, the first b y te of ad526 3 is a slave ad dress b y te. it has a 7 - bit slave a ddr ess and a r/ w bit. t he 5 msbs are 010 11 an d the foll o w in g t w o bits are determ i ne d b y the state of the ad0 an d ad1 pi ns of the devic e. ad0 and ad 1 al lo w th e user to pl ace up to four of the i 2 c compatib le d e vices on one bus. t he 2- w i r e i 2 c serial bus prot ocol o perat es as follo w s : 1. t he master initiates data tra n s fer b y esta blis hin g a st ar t conditi on, w h ic h is w h en a hi gh-to- l o w transitio n on th e sda lin e occ u rs w h il e scl i s high (see f i gur e 3a) . t he follo w i ng b y t e is the slav e address b y te w h ich c onsists of the 7-bit slav e addr ess follo wed b y an r/ w b i t (this bit deter mines w h eth e r data w ill be r ead from or w r itten to th e slave devic e). t he slave w h o s e addr ess cor r espo nds to th e transmitted ad dress resp ond s b y p u ll ing th e sda line lo w d u rin g the ninth cl ock pul se (this is termed the ackno w l e d ge b i t). at this stage, all other d e vi ces on the bus rema in idle w h il e the selecte d dev ice w a its for data to be w r itt en to or rea d from its serial re gister. if the r/ w bit is h i gh, the master w i ll rea d from the slav e devic e. on the other ha nd, if the r/ w bit is low , the master w i ll w r ite to the slave d e vice. 2. a w r ite o per ati on conta i ns an ex tra instruction by te more than a re ad op erati on. such an instru ction b y t e in w r ite mo de follo w s t he slav e address b y te . t he first t w o bits(m sb and sec ond msb) of the in struction b y te l abe le d a1 and a0 are the rda c suba ddress selects. t he third msb rs is the mids cale res e t. a l ogic h i gh of this bit move s the w i per of a selected ch an nel to the center tap w h er e r wa = r wb . t h is feature effectivel y w r it es over the co ntents of the re gister an d thus w h e n take n out of reset mode, the rd ac w i ll remain at mids cale. t he fourth msb sd is a shutdo w n bit. a logic hi gh causes the s e l e cted cha n n e l to ope n circuit a t terminal a w h il e shortin g the w i per to termi n a l b. t h is oper ation yi el d s almost 0 : in rheostat mod e or zero volt in pote n tio m eter mode. t h is sd bit serv es the same functio n at the shdn pin exc ept that the shdn pin re acts to active lo w . also, the shdn p i n affects both cha n n e ls as opp ose d to the sd bit w h ic h onl y affects the cha nne l that is bei ng w r itten to. it is importa nt to no te that t he shutdo w n op eratio n does not disturb th e contents of th e register. w hen brou ght out of shutdo wn, the previo us setting w i l l be app lie d to the rdac. t he follo w i n g tw o bits are o2 and o1. t hey are e x tra progr ammab l e logic outp u ts that can be us ed to drive other di gital l o a d s, logic g a tes, led drivers, a nal og s w itc hes, an d so on. t he three lsbs are d on?t care (see t able iia). 3. after ackno w l e dgi ng the instr u ction b y te, the last b y t e in w r ite mode i s the data b y t e . data is trans mitted over the seri al bus in se qu enc es of nine cl oc k pulses (eig ht data bits follo w e d b y a n ackno w l edg e bit). t he transitio ns on the sda li ne m u st occur duri n g the lo w peri od of scl and rem a in sta b le d u rin g the hig h peri od of scl ( s ee t able iia). 4. in the rea d mode, the d a ta b y te fol l o w s im medi atel y after the ackno w l e d g me nt of the slav e addr ess b y te. data is transmi tted over the serial bus in se q uenc es of nine cl ock p u lses (a sl ight differenc e w i th the w r ite mode, w h ere there ar e ei ght data bits foll o w ed b y an rev. p r e 1/23 /03 10
preliminary technical data AD5263 ackno w l e d ge b i t). similarl y, the transitio ns on the sda lin e must occur dur ing th e lo w p e rio d of scl an d remain sta b le duri ng the h i gh perio d of scl (see f i gure 3 b ). 5. w hen al l data bits have b e e n read or w r itten, a st op cond ition is establis he d b y the master. a st op cond ition is def ine d as a lo w - t o -hi gh transiti o n on the sda lin e w h i l e scl is hi gh. in w r ite mode, the master w i ll p u ll th e sd a line h i gh duri ng the tenth cl ock puls e to establis h a stop cond itio n (see f i gur e 3a) . in read mode, the mas t er w i ll issu e a no ackno w l e d ge for the ninth cl ock pul se (i.e., the sda line rem a ins hig h ). t he master w i l l then brin g the sda lin e lo w b e fore the tenth clock p u l s e w h ic h go es hig h to establ is h a st op conditio n (see f i gur e 3 b ). a repeate d w r it e function give s the user fle x i b ilit y to upd ate the rd ac output a n u m ber of times after addr essin g an d instructin g the part onl y o n c e . durin g the w r it e c y c l e, ea ch data b y te w i ll up date the r d ac outp u t. f o r exampl e, after the rdac has ackn o w l e d ged its slav e addr ess an d in struction b y tes, the rdac out put w ill upd ate after these t w o b y tes. if another b y te is w r itten to the rdac w h il e it is still addr essed to a sp e c ific slave devic e w i th the same instructi on, this b y t e w i ll up date the output of the s e lecte d slav e d e vice. if different instructions are ne ed ed, the w r ite mod e h a s to start w i th a ne w sl ave address, instru ction, and d a ta b y te ag ain. si milarl y, a repe ated re ad functio n of t he rdac is als o a llo w e d. r e a d b a ck rd a c v a lu e ad52 63 al lo w s the user to rea d back the rd ac valu es in the rea d mod e . t he chann e l of interest is the on e that is previ ousl y se le cted in the w r ite mode. in the case w her e users ne ed to r ead the r d ac valu es of both chan nels, the y nee d to pr ogram the first chan nel i n the w r ite mode and the n cha n ge to the re ad mode to rea d the first chan nel v a lu e. after that, the y need to ch ang e back to the w r ite mode w i t h the seco nd c han nel s e lecte d and re ad the secon d cha nne l valu e in th e rea d mod e aga in. note that it is not ne cessar y f o r use r s to issue the f r ame 3 data b y t e in the w r it e mode for su b s equ ent rea d b a ck oper atio n. users sho u ld r e fer to t ables iia and iib for the progr ammin g format. a ddition a l progr a m m a ble log i c o u tput ad52 63 featur es add itio nal pr ogramm abl e lo gic outp u ts, o 1 and o 2 , w h i c h can be used to drive a dig i tal lo ad, ana log s w itc h e s , and log i c gat es. o 1 and o 2 defau lt to logic 0. t he logic states of o 1 and o 2 can be progr ammed i n f r ame 2 unde r w r ite mode (see f i gur e iia). t hese log i c outputs h a ve adeq uate curr ent drivi ng capa bil i t y to si nk/source mi lli amper es of loa d . users can also activate o 1 and o 2 in three di fferent w a ys w i t h o u t affectin g the w i p e r settings. t h e y ma y do the follo w i ng: 1. start, slave address b y te, ackno w l e d ge, instruction by te w i th o 1 and o 2 specifi ed, ackno w l e d ge, stop. 2. compl e te the w r ite c y c l e w i th stop, then start, slave address by te, ackno w le dge, instruction by te w i t h o 1 and o 2 specified, ackno w l e dge, stop. 3. do not comp lete the w r ite c y cl e b y not iss u in g the stop, then start, slave ad dress b y te, ackno w l e d ge, instruction by te w i t h o 1 and o 2 specified, ackno w l e d ge, s t op. self-cont a i ned shutdo wn function shutdo w n ca n be activate d b y strobing the shdn pin or progr ammin g the sd bit in th e w r ite mode instruction b y te. in ad ditio n , shutdo w n c an eve n be im plem ented w i t h the devic e di git a l outp u t as sh o w n i n f i gure 5. in this config uratio n, the dev ice w i ll b e shutdo w n d u ring p o w e r up, but users a r e all o w e d to p r ogram the d e v i ce. t hus w hen o 1 is programme d hig h , the device w i ll exit from the shutdo w n mo d e and res p o nd to the ne w setti ng. t h is self- contai ne d shut do w n fu nctio n allo w s abs olut e shutdo w n duri ng po w e r u p , w h ich is cru c ial in hazar do us envir onme n t, w i thout ad di ng e x tra comp on en ts. f i gure 5. shut dow n by inter n al lo gic out put o1 s hdn rpd sda scl multiple de vices on on e bus f i gure 8 sh o w s four ad526 3 d e vices o n the s a me seri al bus. each h a s a different slav e addr ess sinc e the state of their ad0 a nd ad1 pi ns are d i fferent. t h is allo w s eac h rdac w i th in e a ch dev ice to b e w r itten to or read from ind epe nd entl y . t he master device outp u t bus line dr ivers are op en- drai n pull do w n s in a full y i 2 c comp atibl e interface. s d a s c l a d 5 2 6 3 a d 1 a d 0 m a s t e r s d a s c l r p r p + 5 v s d a s c l a d 5 2 6 3 a d 1 a d 0 s d a s c l a d 5 2 6 3 a d 1 a d 0 s d a s c l a d 5 2 6 3 a d 1 a d 0 + 5 d v + 5 v +5 v f i gure 8. multi p le ad 526 3 de vices on one i 2 c bus rev. p r e 1/23 /03 11
preliminary technical data AD5263 level shift for bi-direction a l interf a c e w h ile most ol d s y stems ma y be op erate d at one vo ltag e, a ne w com pon en t ma y be o p timi zed at an other. w hen t w o s y stems o perat e the same sig nal at t w o differ ent voltag es, prop er leve l shi fting is nee de d. f o r instance, one ca n use a 3.3v e 2 prom to interface w i t h a 5v di gita l potenti o meter. a level sh ift scheme is n e e d e d in ord e r to ena ble a bi-d ir ection al comm unic a tion s o that the setting of the digit a l po tentiometer ca n be stored to and retri e ve d from the e 2 prom. f i gure 7 sho w s o ne of th e implem entati o n s . m1 and m2 can be a n y n- ch sig nal fet s or lo w thr e sho l d fdv30 1 n if v dd falls bel o w 2.5v. 3. 3v e 2 pr o m 5v a d 52 82 sd a 1 sc l 1 sda 2 scl 2 rp rp rp r p v dd1 =3 . 3 v v dd2 =5 v d d s s g g m1 m2 f i gure 9. lev el shift for different potenti a l op eratio n level shift for neg a ti ve volt a g e oper a t ion t he digital p o tentiom e ter is p opu lar in l a ser dio de driv er and certa i n tel e commu nicati o n equ ipme nt le vel setting app licati ons. t hese a p p licati o ns are someti mes oper ated bet w e en gr oun d and som e ne gative su pp l y v o ltag e such that the s y stem s can be bi ase d at groun d to avoi d larg e b y pass ca pacit ors w h ic h ma y signific antl y im ped e the ac performa nce. like most di git a l pote n tiom eters, ad526 3 can be co nfig u r ed w i th a n e g a tive sup p l y (s ee f i gur e 10). f i gure 1 0 . bias ed at neg a tive voltag e ho w e v e r, the d i gital i n p u ts must also be lev e l shifted to allo w pro per o perati on sinc e the gro u n d is n o w r e fere nced to the neg ative potentia l. as a result, f i gure 11 sho w s one im plem ent ation w i t h a fe w trans istors a nd a fe w resistors. w hen v in is belo w q3?s threshold value, q3 is off, q1 is off, a nd q2 is on. in this state, vout approac hes 0v. w hen v in is above 2v, q3 is on, q1 is on, and q2 is turned off. in this state v out i s pull ed d o w n t o vss. be w a r e that proper time sh ifting is als o ne ed ed for successful co mmunicati on w i th the devic e. f i gure 1 1 . lev el shift for bi-p olar p o tenti a l o perati o n esd protection all di gital i n p u ts are protecte d w i th a series i nput resistor and p a ral l e l z ener esd structures sho w n in f i gure 1 2 . appl ies to di git a l in put pi ns, sdi/sda, clk/scl, cs /ad0 and shdn . v ss lo g i c 340 : f i gure 1 2a. es d protection of digita l pins a ,b,w v ss f i gure 1 2b. es d protection of resistor t e rmi nals vdd termin a l volt a g e oper a t ing r a n g e t he AD5263 p o sitive v dd a n d negativ e v ss po w e r su ppl y defin es the bo und ar y c o n d itio ns for proper 3 - terminal digit a l pot entio meter oper atio n. suppl y si gn als pres ent on terminals a, b, and w that exc eed v dd or v ss w i ll be clamp ed b y the interna l for w ar d bias ed d i od e s (see f i gure 13). vss v dd a w b v ss f i gure 1 3 . maximu m t e rmina l voltages s e t by v dd & v ss sda scl gnd -5v level shif te d level shif te d rev. p r e 1/23 /03 12
preliminary technical data AD5263 power up sequence since ther e are esd protecti o n dio des that li mit the voltag e compl i ance at termin a ls a, b, and w (see f i gure 13), it is import ant to po w e r v dd /v ss first before ap pl yi ng an y volta ge to termina ls a, b, and w . other w i se, the dio de w i ll b e for w ar d bias ed suc h that v dd /v ss w ill be po w e re d uni ntenti ona ll y and ma y affect the rest of the user?s circu i t. t he ideal p o w e r up sequ enc e is in the foll o w i ng ord e r: gnd, v dd , v ss , digita l inp u ts, and v a/b/ w . t h e order of po w e rin g v a , v b , v w , and digit a l in puts is not importa nt as lon g as the y ar e po w e red after v dd /v ss . l a yout a nd power sup p ly byp a ssi ng it is a good pra c tice to emplo y compact, mini mum-lea d len g th la yo ut d e sig n . t he leads to the inp u t shou ld b e as direct as poss i ble w i t h a mini mum cond ucto r length. ground p a ths shou ld h a ve lo w res i stanc e a nd lo w ind u ctanc e. similar l y , it is a l so a go od pr a c tice to b y pass the po w e r supp lies w i t h q ualit y ca pacit or s for optimum stabilit y. supp l y lea d s to the devic e sh oul d be b y p a ss ed w i th 0.01uf -0.1 uf disc or chi p cer a mics cap a cito rs. lo w - es r 1uf to 10 uf tantalum or e l ect r ol y t ic cap a cito rs shoul d also b e ap pli e d at the suppl ies to minimize a n y transi ent disturb ance an d lo w freq ue nc y rip p l e (see f i gure 1 4 ). notice the d i git a l gro und s hou ld als o be j o in e d remotel y to the ana lo g gro und at o ne po i n t to minimize t he gro u n d bou nce. f i gure 1 4 . pow e r supp ly bypa ssing v logic powe r supply t he AD5263 is capab le of op eratin g at hig h voltag es be yo nd the i n terna l log i c lev e ls, w h ich ar e li mited to oper ate at 5v. as a result, v l needs to b e tied to a separ ate 2.7 to 5.5v source to ensure pr op er digit a l sig nal levels. AD5263 rev. p r e 1/23 /03 13
AD5263 outli ne di mensions dimens io ns sh o w n i n inch es and (mm) rev. p r e 1/23 /03 14

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